A voltage multiplier or a voltage doubler is used for producing an output voltage Vout which is an integer times of the high voltage level of a clock signal. A bootstrap circuit is a type of voltage multiplier with high input impedance.
FIG. 1A schematically illustrates a conventional bootstrap circuit, in which the input terminal is at a high voltage level. FIG. 1B schematically illustrates a conventional bootstrap circuit, in which the input terminal is at a low voltage level.
As shown in FIGS. 1A and 1B, the conventional bootstrap circuit 10 includes a first P-type transistor P1, a first N-type transistor N1, a second P-type transistor P2, a first inverter INV1, and a first bootstrap capacitor CB1.
As shown in FIG. 1A, the gate terminal of the first P-type transistor P1 and the gate terminal of the first N-type transistor N1 are both electrically connected with an input terminal Sin of the bootstrap circuit 10. Consequently, the on/off statuses of the first P-type transistor P1 and the first N-type transistor N1 are determined according to the voltage at the input terminal Sin of the bootstrap circuit 10.
Moreover, the input terminal of the first inverter INV1 is also electrically connected with the input terminal Sin of the bootstrap circuit 10. The output terminal of the first inverter INV1 is electrically connected with a first end of the first bootstrap capacitor CB1 through a first node s1. A second end of the first bootstrap capacitor CB1 is electrically connected with the drain terminal of the second P-type transistor P2 and the source terminal of the first P-type transistor P1 through a second node s2.
Moreover, the drain terminal of the first P-type transistor P1, the drain terminal of the first N-type transistor N1 and the gate terminal of the second P-type transistor P2 are collectively connected with the output terminal Sout of the bootstrap circuit 10. The source terminal of the second P-type transistor P2 is electrically connected with a power voltage Vdd. The source terminal of the first N-type transistor N1 is electrically connected with a ground terminal. The voltage at the ground terminal is equal to a ground voltage (Vss=GND=0V).
As the clock signal CLK inputted into the input terminal Sin of the bootstrap circuit 10 is changed, the voltage at the output terminal Sout of the bootstrap circuit 10 is changed. The bootstrap circuit 10 of FIG. 1A and the bootstrap circuit 10 of FIG. 1B are substantially identical. However, the input voltage Vin of the clock signal CLK in the bootstrap circuit 10 of FIG. 1A is at the high voltage level (i.e. Vin=Vdd), but the input voltage Vin of the clock signal CLK in the bootstrap circuit 10 of FIG. 1B is at the low voltage level (i.e. Vin=0 volt). The operations of the transistors, capacitor, inverter and nodes included in the bootstrap circuit 10 as shown in FIGS. 1A and 1B will be illustrated in more details with reference to FIG. 1C.
FIG. 1C is a schematic timing waveform diagram illustrating associated voltage signals processed in the bootstrap circuit of FIGS. 1A and 1B. As shown in FIG. 1C, the clock signal CLK inputted into the input terminal of the bootstrap circuit has a low voltage level equal to the ground voltage (0 volt) and a high voltage level equal to the power voltage Vdd.
Since the clock signal CLK is inputted into the bootstrap circuit 10 through the input terminal Sin of the bootstrap circuit, the voltages at the gate terminal of the first P-type transistor P1, the gate terminal of the first N-type transistor N1 and the input terminal of the first inverter INV1, which are electrically connected with the input terminal Sin of the bootstrap circuit, are also changed with the voltage level change of the clock signal CLK. Consequently, the operations of the bootstrap circuit 10 are varied in response to the voltage level change of the clock signal CLK.
In FIG. 1C, the first waveform (i.e. the topmost waveform) denotes the change of the voltage Vin at the input terminal Sin of the bootstrap circuit, the second waveform (i.e. the waveform under the first waveform) denotes the change of the voltage Vout at the output terminal Sout of the bootstrap circuit, the third waveform (i.e. the waveform under the second waveform) denotes the change of the voltage Vs1 at the first node s1, and the fourth waveform (i.e. the bottommost waveform) denotes the change of the voltage Vs2 at the second node s2.
For example, the clock signal CLK inputted into the bootstrap circuit is initially at the low voltage level. The clock signal CLK is switched to be at the high voltage level during a first time period T1, and the clock signal CLK is switched to be at the low voltage level during a second time period T2. The operations of the conventional bootstrap circuit will be illustrated by referring to FIG. 1A and FIG. 1B and the first time period T1 and the second time period T2 of FIG. 1C.
Please refer to FIG. 1A and the first time period T1 of FIG. 1C. In a case that the clock signal CLK is at the high voltage level during the first time period T1, the voltage Vin at the input terminal Sin of the bootstrap circuit is also at the high voltage level. Since the voltage at the gate terminal of the first N-type transistor N1 is at the high voltage level, the first N-type transistor N1 is turned on. Since the voltage at the gate terminal of the first P-type transistor P1 is at the high voltage level, the first P-type transistor P1 is turned off.
As the first N-type transistor N1 is turned on, the output terminal Sout of the bootstrap circuit is connected with the ground terminal Vss through the first N-type transistor N1. Consequently, as shown in FIG. 1A, a current is generated from the output terminal Sout of the bootstrap circuit and flows to the ground terminal Vss through the first N-type transistor N1. Moreover, as shown in FIG. 1C, the voltage Vout at the output terminal Sout of the bootstrap circuit is maintained at the low voltage level (0 volt) during the first time period T1.
Since the gate terminal of the second P-type transistor P2 is electrically connected with the output terminal Sout of the bootstrap circuit, the voltage at the gate terminal of the second P-type transistor P2 is 0 volt. Under this circumstance, the second P-type transistor P2 is turned on. As the second P-type transistor P2 is turned on, the voltage at the drain terminal of the second P-type transistor P2 is equal to the power voltage Vdd. Consequently, as shown in FIG. 1C, the voltage at the second node s2 is maintained at the power voltage Vdd during the first time period T1.
On the other hand, in a case that the clock signal CLK is at the high voltage level, the voltage at the first node s1 (the output voltage of the first inverter INV1) is at the low voltage level. Consequently, as shown in the third waveform of FIG. 1C, the voltage at the first node s1 is 0 volt during the first time period T1.
From the above discussions, since the first and the second ends of the first bootstrap capacitor CB1 are respectively connected with the first node s1 and the second node s2, the voltages at the first end of the first bootstrap capacitor CB1 and the second end of the first bootstrap capacitor CB1 are respectively equal to 0 volt and Vdd. Consequently, as shown in FIG. 1A, the power voltage generates a current, and the current flows through the second P-type transistor P2 to charge the first bootstrap capacitor CB1.
The behaviors of the sub-bootstrap circuit 20 during the second time period T2 will be illustrated with reference to FIGS. 1B and 1C. Since the clock signal CLK is at the low voltage level during the second time period T2, the voltage at the first node s1 (the output voltage of the first inverter INV1) is at the high voltage level. Since the first bootstrap capacitor CB1 is charged during the first time period T1, the voltage difference between the two ends of the first bootstrap capacitor CB1 is equal to a capacitor voltage Vdd. Consequently, when the voltage at the first node s1 is increased to Vdd during the second time period T2, the voltage at the second node s2 is correspondingly increased to a first superimposed voltage, which is equal to 2×Vdd (i.e. Vdd+Vdd=2×Vdd).
On the other hand, in response to the low voltage level of the clock signal CLK, the first P-type transistor P1 is turned on, and the first N-type transistor N1 is turned off. When the first P-type transistor P1 is turned on, a current flows to the output terminal Sout of the bootstrap circuit 10 through the second node s2. Under this circumstance, the voltage at the output terminal Sout of the bootstrap circuit 10 is also 2×Vdd. Consequently, the output terminal Sout of the bootstrap circuit 10 is changed from 0 volt (during the first time period T1) to 2×Vdd (during the second time period T2).
Moreover, since the gate terminal of the second P-type transistor P2 is electrically connected with the output terminal Sout of the bootstrap circuit 10, the voltage at the gate terminal of the second P-type transistor P2 is also 2×Vdd. Consequently, the second P-type transistor P2 is turned off during the second time period T2.
The operations of the conventional bootstrap circuit 10 as mentioned above are in an ideal state. In practical applications, since the output terminal Sout of the bootstrap circuit 10 is connected with a load circuit, the load circuit generates a load capacitance between the output terminal Sout of the bootstrap circuit 10 and the ground terminal. Moreover, the conventional bootstrap circuit 10 has the inherent parasitic capacitance. In a case that the load capacitance of the load circuit and the parasitic capacitance are included in the conventional bootstrap circuit 10, the operations of the conventional bootstrap circuit 10 are adversely affected.
FIG. 1D schematically illustrates a conventional bootstrap circuit with a load capacitance. In comparison with the bootstrap circuit as shown in FIGS. 1A and 1B, the conventional bootstrap circuit 10 in FIG. 1D has a load capacitance CL, which is indicated as a dotted line. The load capacitance CL represents the sum of the load capacitance of the load circuit and the parasitic capacitance.
When the load capacitance CL is taken into consideration, the voltage Vout at the output terminal Sout of the bootstrap circuit 10 is influenced by the load capacitance. The voltage Vout at the output terminal Sout of the bootstrap circuit 10 may be calculated by the following equation (1).
                              V          out                =                              2            ⁢                                                  ⁢                          V              DD                        ×                                          C                                  B                  ⁢                                                                          ⁢                  1                                                                              C                                      B                    ⁢                                                                                  ⁢                    1                                                  +                                  C                  L                                                              =                      2            ⁢                                                  ⁢                          V              DD                        ×                          1                                                1                  ⨯                                      C                    L                                                  /                                  C                                      B                    ⁢                                                                                  ⁢                    1                                                                                                          (        1        )            
In other words, in a case that the clock signal CLK is at the high voltage level, the high voltage level at the output terminal Sout of the bootstrap circuit 10 is not ideally equal to 2×Vdd. Whereas, the high voltage level at the output terminal Sout of the bootstrap circuit 10 is determined according to a ratio of the load capacitance CL to the capacitance of the first bootstrap capacitor CB1.
As the ratio CL/CB1 is decreased, the influence of the ratio CL/CB1 on the output voltage Vout is decreased, and the efficiency of the bootstrap circuit 10 is increased. As the ratio CL/CB1 is increased, the influence of the ratio CL/CB1 on the high voltage level of the output voltage Vout is increased, and the efficiency of the bootstrap circuit 10 is decreased.
Due to the low mobility property, the parasitic capacitance at the high frequency is increased and the load capacitance CL is increased correspondingly. In other words, the high-frequency applications of the conventional bootstrap circuit 10 are affected by the parasitic capacitance and the load circuit. Under this circumstance, the high voltage level at the output terminal Sout of the bootstrap circuit 10 fails to be actually increased to 2×Vdd.